With the advancement of artificial intelligence (AI), deep neural networks (DNN), ADAS, and high-performance computing (HPC), there is an ever-increasing demand for higher memory bandwidth. Along with the large amount of data generated by these applications, the memory sub-system plays a crucial role in the overall performance.
TSS GDDR6 PHY utilizes state-of-the-art architecture in full custom analog mixed-signal design to overcome the problem of long-term impedance drift and clock phase drift, allowing impedance and clock phase updates without the need to interrupt data traffic. The programmable timing PHY boundary combines flexibility with analog precision. The result is ultra low PHY read/write latency between memory controller and the GDDR6 DRAM without sacrificing performance.
The TSS GDDR6 PHY IP, operating at up to 16Gbps data rates in a 32-bit 2-channel configuration, provides a peak memory bandwidth of 64GB/s.
TSS understands that aside from performance and power, the implementation requirement at the system level such as package stack up layer count and PCB layer count are also crucial factors to consider at the product level. This is why the TSS team designed the GDDR6 PHY with the lowest system level implementation cost in mind, allowing cost sensitive applications to reap the benefits of this blazing fast memory standard.
DFI4.0 interface to memory controller
PHY-independent DRAM initialization and training - no memory controller involved
Max Data Rate Support
Maximum data rate of 16Gbps
Integrated proprietary microcontroller
Firmware based PHY training, characterization, debug, and production testing
x16, x8, and PC modes
Low frequency RDQS mode
Continuous IO impedance and timing phase adjustment without traffic interruption
TX equalization and RX CTLE/DFE improves WRITE and READ eye margins
TSMC N12 GDDR6 PHY
Silicon Proven: Yes