At The Six Semiconductor (The Six), our vision is to offer best in class mixed-signal IP combined with exceptional service, thus enabling SOC companies to bring their product to market in highest quality and shortest time.  When compared to competitors, our IP achieve higher performance at lower power and area, while offering the flexibility and ease of integration to our customers.  Our team is highly experienced with a long list of achievements and accomplishments in the semiconductor industry.

We strongly believe in a culture of transparency and trust.  By ensuring important information are readily accessible, we entrust our staff to make the best decisions resulting in superior products and customer service.  We also foster a continuous learning environment with an emphasis on a well-rounded career.  Our compensation and benefits package is very competitive as we believe best talents should be rewarded accordingly.  We welcome you to be part of this fast-growing team making an impact in the industry.

As a digital design engineer at The Six, you will be responsible for the design and bring-up of our memory PHY IP.  You will be involved in the whole design process, from architecture to GDS realization.  You will also be actively engaged with customers to ensure successful integration into their SOC.


  • Architectural design including interface definition, power and frequency state logic, link training algorithm, phase tracking algorithm, PLL and DLL calibration, data path optimization and DFT
  • Implementation of PHY and Testchip RTL logic in Verilog
  • Functional modeling of PHY custom circuits in Verilog
  • Design specification for verification team and external customer
  • Review test plan and verification environment
  • Participation in testplan development
  • Testchip and PHY bring-up flow development
  • Customer integration and bring-up support


  • Bachelor/Master in Electrical or Computer Engineering
  • Extensive RTL design experience in Verilog/VHDL
  • Deep understanding of timing constraints and clock domain crossing (CDC)
  • Knowledge of full ASIC design flow including synthesis, place and route, scan interstion, etc
  • Experience with design or validation of memory interfaces such DDR, LPDDR, HBM and GDDR
  • Proficient in scripting languages (Perl, Python, Tcl, etc)

We’re looking to fill multiple positions with different level of experience from Junior to Senior Staff.  If you love to work and grow in a fast paced environment, please send your resume to  We look forward to talking to you.