About the Role
As a digital design engineer at The Six, you will be responsible for the design and bring-up of our memory PHY IP. You will be involved in the whole design process, from architecture to GDS realization. You will also be actively engaged with customers to ensure successful integration into their SOC.
Responsibilities
Architectural design including interface definition, power and frequency state logic, link training algorithm, phase tracking algorithm, PLL and DLL calibration, data path optimization and DFT
Implementation of PHY and Testchip RTL logic in Verilog
Functional modeling of PHY custom circuits in Verilog
Design specification for verification team and external customer
Review test plan and verification environment
Participation in testplan development
Testchip and PHY bring-up flow development
Customer integration and bring-up support
Requirements
Bachelor/Master in Electrical or Computer Engineering
Extensive RTL design experience in Verilog/VHDL
Deep understanding of timing constraints and clock domain crossing (CDC)
Knowledge of full ASIC design flow including synthesis, place and route, scan interstion, etc
Experience with design or validation of memory interfaces such DDR, LPDDR, HBM and GDDR
Proficient in scripting languages (Perl, Python, Tcl, etc)