About the Role
As a Digital Design Engineer Intern at TSS, you will be working closely with our Digital Design team in which you will learn about RTL design and functional modeling of PHY custom circuits
Responsibilities
Implementation of PHY and Testchip RTL logic in Verilog
Functional modeling of PHY custom circuits in Verilog
Participation in testplan development
Testchip and PHY bring-up flow development
C / Python test development
Developing methodology and automation processes
Requirements
Currently in the process of obtaining a Bachelor’s, Master’s, or Doctorate in Electrical Engineering, Computer Engineering, or related field
Good grasp of electrical circuits concepts in both transistor and logic gate level
Excellent communication skills and problem-solving skills
Team player and willingness to learn
Programming, HDL, and scripting languages (C/C++, Verilog, Perl, Python, Tcl, etc) is an asset
Knowledge of RTL design and high-speed memory (GDDR/LPDDR/HBM) interfaces is a plus