|TSS PHY||Foundry Tech Node||Availability||Silicon Proven|
|GDDR6 PHY||TSMC N12 FFC||Now||Yes|
|LPDDR54 PHY||Samsung Foundry 14LPP/LPU||Now||Q3 2021|
|LPDDR54 PHY||TSMC N12 FFC||Now||Q4 2021|
|HBM3 PHY||TBD||Q2 2022||Q2 2022|
Consumer mobile and edge devices are processing large amounts of data in today’s applications, ranging from video processing, mobile gaming, to AI-based image recognition. As a result of these advancements, the memory sub-system plays a crucial role in the overall performance.
The TSS LPDDR54 PHY utilizes state-of-the-art architecture to maximize timing and voltage margins over process, voltage and temperature variations, while minimizing interruption to data traffic.
Built-in power management logic and advanced PLL design allows aggressive power state management and optimal system power usage.
At the system level, the LPDDR54 OPHY was designed with minimal package substrate layer and PCB layer count in mind. This enables the integration of a LPDDR memory sub-system solution in cost sensitive applications, such as consumer edge devices, digital set-top-box and TV, SSD controllers, and application processors.
- JESD209-5A (LPDDR5), JESD209-4C (LPDDR4), JESD209-4-1(LPDDR4X) compliant
- Operating speed up to 6400Mbps in LPDDR5 and 4266Mbps in LPDDR4(x)
- Continuous IO impedance and timing phase updates with no traffic interruption
- Support for x16, x8, and PC modes
- DFI 4.0 interface to memory controller
- PHY-independent initialization of DRAM and training – no memory controller involved
- TX pre-emphasis and de-emphasis and RX decision-feedback equalization(DFE) improves WRITE and READ eye margins respectively
- Multiple frequency set points (FSP) enables rapid frequency change
- Ultra low READ/WRITE latency with programmable PHY boundary timing
The TSS LPDDR54 PHY is available in Samsung 14nm and TSMC 12nm technologies