DDR PHY design is in our DNA
TSS is actively developing high-performance memory PHY in various technology nodes
JESD-209-5B LPDDR5X/LPDDR5
JESD209-4 LPDDR4X/LPDDR4
Operating speed up to 8533Mbps
x16 and x32 channel support
Multi-rank support up to 4 ranks
Supports up to 3 frequency set points (FSPs)
PHY-independent DRAM initialization and training - no memory controller
Firmware-based training with proprietary microcontroller
Multiple training types with various training durations
Highly configurable hard-IP floorplan with IO swizzle
JESD238 HBM3 compliant
Supports up to 16 independent and asynchronous channels, each with 2x32-bit DWORD pseudo-channels
Multiple frequency set points (FSPs)
Data and command/address parity
Automatic interconnect redundancy remapping
Firmware-based training with proprietary microcontroller
Firmware-based API to work with DRAM's IEEE 1500 for training and testing
Fully integrated memory controller within each PHY channel
JESD-250C GDDR6
Operating speed up to 16Gbps
Support for x16, x8, and PC modes
DFI4.0 interface to memory controller with extension for GDDR6 support
PHY-independent DRAM initialization and training - no memory controller
Multiple frequency set points (FSPs) enabling rapid frequency change
Ultra low READ/WRITE latency with programmable PHY boundary timing
Continuous IO impedance and timing phase updates with no traffic interruption