LPDDR54 PHY
Overview
Consumer mobile and edge devices are processing large amounts of data in today’s applications, ranging from video processing, mobile gaming, to AI-based image recognition. As a result of these advancements, the memory sub-system plays a crucial role in the overall performance.
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The TSS LPDDR54 PHY utilizes state-of-the-art architecture to maximize timing and voltage margins over process, voltage and temperature variations, while minimizing interruption to data traffic.
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Built-in power management logic and advanced PLL design allows aggressive power state management and optimal system power usage.
At the system level, the LPDDR54 OPHY was designed with minimal package substrate layer and PCB layer count in mind. This enables the integration of a LPDDR memory sub-system solution in cost sensitive applications, such as consumer edge devices, digital set-top-box and TV, SSD controllers, and application processors.
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JEDEC Compliant
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JESD209-5B (LPDDR5x)
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JESD209-5A (LPDDR5)
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JESD209-4-1 (LPDDR4x)
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JESD209-4C (LPDDR4)
MC Integration
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DFI 5.1 interface to memory controller
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PHY-independent DRAM initialization and training - no memory controller involved
Max Data Rate Support
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Supports the maximum data rate offered by each LPDDR standard
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Maximum data rate of 8533Mbps for LPDDR5x
Embedded MCU
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Integrated proprietary microcontroller
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Firmware based PHY training, characterization, debug, and production testing
PHY Configuration
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x16 and x32 DQs per DFI channel
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x8/x16 mode support
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Optional dual-rank and quad-rank configuration to extend memory capacity
Analog Features
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Continuous IO impedance and timing phase adjustment without traffic interruption
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TX equalization and RX DFE improves WRITE and READ eye margins
LPDDR54 PHY
Availability
TSMC N7/N6 LPDDR5x/5/4x/4 PHY
Availability: Now
Silicon Proven: Yes
TSMC N12 LPDDR5/4x/4/ PHY
Availability: Now
Silicon Proven: Yes
TSMC N22 LPDDR4 PHY
Availability: Now
Silicon Proven: Yes
Samsung 14LPP LPDDR5/4x/4 PHY
Availability: Now
Silicon Proven: Yes
Samsung 14LPU LPDDR5/4x/4 PHY
Availability: Now
Silicon Proven: TBD
Contact
Looking for the optimal memory sub-system for your next SoC? Get in touch to learn more.