An analog mixed-signal expert and leader who successfully developed GDDR5 PHY, DDR3 PHY, ADC/DAC, HS/GPIO, high voltage tolerant IO, GPU ESD and a 60GHz RF chip. He was a sub-group technical lead for the Displayport Standards Workgroup for defining part of the DP1.2 specification. Mr. Fung is a graduate of B.A.Sc and M.Eng degrees in Electrical Engineering from the University of Toronto. He is also a registered professional engineer of Ontario and holds 11 US patents.
A system architect who is an expert in generations of PHYs including GDDR5, DDR4/5, LPDDR4/5, and MIPI CSI-2 and D-PHY. A master RTL designer with extensive knowledge in different industry standards and a member of the MIPI standards committee. Mr. Lau earned B.A.Sc and M.Eng degrees, both in Electrical Engineering from the University of Toronto and a holder of 2 US patents.
An all around analog mixed-signal circuit design engineer who is experienced in PLL, DLL, CDR, ADC, DAC and LDO designs in multiple foundries and technologies. A senior member of IEEE who worked and consulted with various leading edge high tech companies across the globe. Mr. Chan is a graduate of a B.A.Sc degree in Electrical Engineer from the University of Waterloo and a M.Sc degree in IC Design Engineering from the Hong Kong University of Science and Technology. He is also a registered professional engineer of Ontario and holds 3 US patents.
Co-founder, VP Engineering
An analog mixed signal circuit expert in low-phase noise high-speed clock generation, PLL, DLL and GDDR5 PHY design. A master in cad and design flow has proven vital in many successful tapeouts with multiple foundries and technologies. Mr. Poon is a graduate of B.A.Sc and M.A.Sc degrees in Electrical Engineering from the University of Toronto and holds one US patent.
Co-founder, Chief Scientist
A seasoned veteran in high speed IO circuit design including PCIE Gen 1/2, DDR2/3/4/5, LPDDR4/5, GDDR5, HBM2, MIPI CSI-2 & D-PHY, and PLL/DLL. He is a true schematic and layout co-design expert who focuses on area and power reduction while maximizing circuit performance at the same time. Mr. Ng has a B.A.Sc degree in Electrical Engineering from the University of Toronto and holds 2 US patent.
Mr. Ho is an ASIC design zealot with years of expertise in large-scale SoC development and IP integration. His extensive knowledge spans the whole spectrum of ASIC implementation cycle from architecture design, functional/performance modelling, to silicon implementation and production testing. He received a B.A.Sc. degree in Electrical Engineering from the University of Toronto and is a holder of 6 US patents.