About the Role
As a Digital Implementation Engineer, you will be responsible for the digital physical design and chip implementation of our memory PHY IP and test chips.
Responsibilities
Develop, implement and deliver memory PHY IP and test chips across a broad range of foundry process technologies, primarily low geometry FinFet nodes
Tasks to include timing constraint development, synthesis, power optimization, STA, equivalence checking, generation of timing and physical models
Using industry standard EDA tools and techniques to develop the highest quality memory PHY IP with aggressive PPA targets
Develop and automate our digital implementation flows
Implement strong design quality checking methodologies to ensure our customers consistently receive the highest quality memory PHY IP
Support our customers in integrating our IP products
Requirements
Bachelor/Master in Electrical or Computer Engineering
Experience of implementing digital designs from RTL through synthesis to signoff, including synthesis, DFT, PnR, STA, DRC/LVS, EMIR analysis, equivalence checking etc.
Deep understanding of timing constraints, clock domain crossing strategies, and foundry process technologies
Understanding of signoff and release requirements of digital semiconductor IP
Experience of major EDA tools and design methodologies for high-speed digital semiconductor IP
Working knowledge of scripting for automation, primarily in TCL, Perl, and Python
Strong analytical, problem-solving, and communication skills