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DDR PHY design is in our DNA

TSS is actively developing high-performance memory PHY in various technology nodes

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JESD209-5C LPDDR5X/LPDDR5

JESD209-4-1A LPDDR4X

JESD209-4D LPDDR4

DFI5.1 interface compliant

Operating speed up to 8533Mbps

x16 and x32 channel support

Multi-rank support up to 4 ranks

Supports multiple frequency set points (FSPs) for rapid frequency change to maximize power savings

PHY-independent DRAM initialization and training

Firmware-based training with embedded microcontroller

Optimized training type and duration for multiple systems and package options

Highly configurable hard-IP floorplan with IO swizzle

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JESD238A HBM3

Supports up to 16 independent and asynchronous channels, each with 2x32-bit DWORD pseudo-channels

Multiple frequency set points (FSPs)

Data and command/address parity

Automatic interconnect redundancy remapping

Firmware-based training with embedded microcontroller

Firmware-based API to work with DRAM's IEEE 1500 for training and testing

Fully integrated memory controller within each PHY channel

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JESD250D GDDR6

Operating speed up to 16Gbps

Support for x16, x8, and PC modes

DFI4.0 interface to memory controller with extension for GDDR6 support

PHY-independent DRAM initialization and training

Multiple frequency set points (FSPs) enabling rapid frequency change

Continuous IO impedance and timing phase updates with no traffic interruption

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