top of page
iStock-1316117848.jpg

LPDDR5X/5/4X/4 PHY

Overview

Consumer mobile and edge devices are processing large amounts of data in today’s applications, ranging from video processing, mobile gaming, to AI-based image recognition.  As a result of these advancements, the memory sub-system plays a crucial role in the overall performance.

The TSS LPDDR5X/5/4X/4 PHY utilizes state-of-the-art architecture to maximize timing and voltage margins over process, voltage and temperature variations, while minimizing interruption to data traffic.

Built-in power management logic and advanced PLL design allows aggressive power state management and optimal system power usage.

 

At the system level, the LPDDR5X/5/4X/4 PHY was designed with minimal package substrate layer and PCB layer count in mind.  This enables the integration of a LPDDR memory sub-system solution in cost sensitive applications, such as consumer edge devices, digital set-top-box and TV, SSD controllers, and application processors.

When integrated together with OPENEDGES' memory controller (OMC), users can expect a high performance total memory subsystem solution that is fully co-validated and ready for deployment at the SoC level. 

Supports JEDEC-Compliant DRAM

  • JESD209-5C (LPDDR5x/5)

  • JESD209-4-1A (LPDDR4x)

  • JESD209-4D (LPDDR4)

MC Integration

  • DFI 5.1 interface to memory controller

  • PHY-independent DRAM initialization and training

  • Fully verified with Openedges' memory controller for rapid integration turnaround

Max Data Rate Support

  • Supports the maximum data rate offered by each LPDDR standard

  • Maximum data rate of 8533Mbps for LPDDR5x

Embedded MCU

  • Integrated microcontroller adds a high degree of flexibility to PHY training and automated calibration

  • Firmware based PHY training, characterization, debug, and production testing

PHY Configuration

  • x16 and x32 DQs per DFI channel

  • x8/x16 mode support

  • Optional dual-rank and quad-rank configuration to extend memory capacity

Analog Features

  • Continuous IO impedance and timing phase adjustment without traffic interruption

  • TX equalization and RX DFE improves WRITE and READ eye margins

  • Per-bit timing deskew capability on DQ and CA signals for optimal per bit timing margin

LPDDR5X/5/4X/4 PHY
Availability

TSMC N7/N6 LPDDR5x/5/4x/4 PHY

Availability: Now

Silicon Proven: Yes

TSMC N12 LPDDR5x/5/4x/4/ PHY

Availability: Now

Silicon Proven: Yes

TSMC N16 LPDDR5x/5/4x/4/ PHY

Availability: Now

Silicon Proven: 2024 Q3

TSMC N22 LPDDR4 PHY

Availability: Now

Silicon Proven: Yes

Samsung 5LPE LPDDR5X/5/4x/4 PHY

Availability: Now

Silicon Proven: Q1 2024

Samsung 14LPP LPDDR5/4x/4 PHY

Availability: Now

Silicon Proven: Yes

From our Customers

"Our experience with OPENEDGES’ team has been outstanding, enabling seamless silicon bring-up, which can be quite complicated.  We are excited that the released SoC has met and even exceeded our expectations, reaching our required maximum data rates with only half the footprint of other solutions, and we are now looking forward to mass production within a short time. This combination LPDDR5/4x/4 IP solution support all required features of the LPDDR specifications, enabling our team to achieve the necessary functionality and flexibility in our SoC.”

Daniel Kim, CEO of Novachips

novachips logo_edited.jpg
asicland logo.png
Aisin Logo_edited.png

Contact

Looking for the optimal memory sub-system for your next SoC? Get in touch to learn more.

  • Facebook
  • Twitter
  • LinkedIn
  • Instagram

Thanks for submitting!

bottom of page