HBM3 PHY
Overview
For ultra-high memory-intensive applications with large memory capacity requirements, HBM3 memory sub-system is undoubtedly the best solution to choose from. It is most suitable in the fields of artificial intelligence (AI), machine learning (ML), and general-purpose graphics processing units (GPGPU).
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The TSS HBM3 PHY utilizes state-of-the-art architecture to maximize timing and voltage margins over process, voltage and temperature variations, while minimizing interruption to data traffic.
The HBM3 PHY IP has the capability to support up to 16 independent and asynchronous channels, each with 2x32-bit DWORD pseudo-channels. Additional features include multiple frequency set points (FSPs), DBI, ECC, SEV, and Parity (data and command/address parity), as well as lane repair, also known as Interconnect Redundancy Remapping, which detects, repairs, and remaps repairable interconnect issues automatically, making them transparent to the memory controller.
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Supports JEDEC-Compliant DRAM
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JESD238A (HBM3)
MC Integration
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Integrated HBM3 memory controller as a single hard-IP
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DFI5.1 interface with memory controller
Max Data Rate Support
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Maximum data rate of 8.4Gbps
Embedded MCU
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Integrated proprietary microcontroller
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Firmware based PHY training, characterization, debug, and production testing
PHY Features
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16 independent and asynchronous channels
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Multiple frequency set points (FSPs)
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Interconnect redundancy remapping
Analog Features
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Continuous IO impedance and timing phase adjustment without traffic interruption
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Programmable TX drive strengths and RX DFE improves WRITE and READ eye margins
HBM3 PHY
Availability
TSMC N7 HBM3 PHY
Availability: Now
Silicon Proven: Now
TSMC N6 HBM3 PHY
Availability: Upon request
Silicon Proven: TBD
Contact
Looking for the optimal memory sub-system for your next SoC? Get in touch to learn more.